1. Field of the Invention
This invention relates to a logic gate which is a variation of ECL logic and, more particularly, relates to a logic gate circuit capable of performing logic functions on the complement of one or more of the input variables.
2. Discussion of Background and Prior Art
Circuit designers are able to choose from a variety of logic families as they design integrated circuits. Their selection will be based on such criteria as speed, processes available inhouse, compatibility with related circuits and power consumption. For digital integrated circuits based on bipolar processes a designer can choose from the major logic families, e.g. from resistor-transistor logic, diode-transistor logic, transistor-transistor logic, emitter-coupled logic, integrated injection logic and integrated Schottky logic, as well as from a host of specialized logic families such as nonthreshold logic, emitter function logic, complementary transistor logic, and others. See, e.g., D. A. Hodges et al, Analysis and Design of Digital Integrated Circuits, Chapter 7, "Bipolar Digital Gate Circuits", (McGraw-Hill 1983); H. W. Gschwind et al, "Bipolar Logic Families", Chp. 4.4 in Design of Digital Computers, pp. 64-108 (Springer-Verlag 1975); Z. E. Skokan, "Logic Gate", U.S. Pat. No. 3,643,109; A. W. Peltier, "Schottky Diode--Complementary Transistor Logic", U.S. Pat. No. 3,987,310; and J. H. Gilder, "New Bipolar Technologies to Compete With CMOS and ECL", Electronic Design, v. 24, No. 5, pp. 18-19, Mar. 1, 1976. Each logic family has its own advantages and may be preferred for specific applications. For example, emitter-coupled logic is preferred for high performance applications and transistor-transistor logic for medium performance at low cost.
Emitter-coupled logic (ECL) is widely utilized. ECL results in high performance products and has the shortest propagation delay of any bipolar logic form. ECL logic is preferred for such diverse applications as large computers, instrumentation and telecommunications systems. The standard gate for ECL is an OR/NOR gate of the type shown in FIG. 1. See also W. C. Seelbach, "Emitter-Coupled Logic", Chp. 3 in Integrated Circuits Applications Handbook (Wiley 1983). In FIG. 1, the input signals B and C are provided at the bases of input transistors 10 and 11. The OR output of the two input signals is provided at the emitter of OR output transistor 14 while the NOR of the two signal values is provided at the emitter of NOR output transistor 13. The voltage levels of the input signals B, C are standard ECL levels whereby an acceptable logic 1 is signified by a voltage within a pass band of about -0.78 volts to about -1.001 volts and an acceptable logic 0 is signified by a voltage within a pass band of about -1.635 volts to about -1.850 volts. The voltage VBB provided at the base of reference transistor 12 is set midway between the mean ECL level for a logic 0 (-1.7 volts) and the mean ECL level for a logic 1 (-0.9 volts), i.e., at a level of -1.3 volts. Thus, the current between the supply line V.sub.CC and the low potential line V.sub.EE steers between reference transistor 12 or one or more of input transistors 10 and 11 thereby producing the OR and NOR outputs.
In the normal operation of a standard ECL OR/NOR gate, the ORing and NORing is performed on the input values as received, i.e. directly on the signals B and C, etc. As stated above, these input values will possess voltages within pass bands of about -0.78 to about -1.001 volts if they are to be recognized as a logic 1 or of about -1.635 to about -1.850 volts if they are to be recognized as a logic 0. It is at times desired to perform logical operations in ECL circuits on the complement of an available logic signal. In a logic sense the complement of an input is the opposite value, i.e., the complement of a logic 0 is a logic 1; in a voltage sense the voltage will be shifted so that while the original input fits within one of the pass bands, the complement will fit within the other pass band. Thus, an input representing a logic 1 would originally have a voltage of -0.78 to -1.001 volts; its complement would necessarily be shifted by as little as -0.634 volts or as much as -1.07 volts to fit within the pass band for a logic 0. Similarly, an input representing a logic 0 would originally have a voltage of -1.635 volts to - 1.850 volts and its complement would be shifted by as much as +1.07 volts or as little as +0.634 volts to fit within the pass band for an acceptable logic 1. In circuit terms, as shown in FIG. 3, it is sometines desired to perform a NOR operation on several input signals, one or more of which is complemented. There is no way in any of the bipolar logic families including ECL to provide such complemented inputs without utilizing a separate inverter stage or without utilizing Cascode circuitry of the type shown in FIG. 2. In either case, the inversion would be obtained at the cost of delay or at the expense of power. Thus, with conventional ECL logic it would be required to add an inverter stage to produce the inversion of the logic signal so that it can be introduced along with other inputs into a logic circuit. See, e.g., H. W. Gschwind et al, Design of Digital Computers, FIG. 4.39(c) at p. 91 (Springer-Verlag 1975). While such an approach is straightforward to implement, it involves the delay of an additional inverter stage, consumes additional power and requires additional chip area for the added inverter.
In the prior art in lieu of providing an individual inverter stage 46 as shown in FIG. 3, logic functions incorporating the complement of one or more input signals may be performed by dual level or Cascode logic as shown in FIG. 2. Here, the two input signals A and B are operated upon to produce the logic outputs, Z1=A.B+A.B and Z2=A.B+A.B. Such an approach requires the use of numerous additional transistors, requires an additional reference voltage (V.sub.BB2 as well as V.sub.BB1) and consumes more power than desired, because the supply voltage V.sub.EE must be made more negative in order to support two levels of logic instead of one.
It is therefore an object of the present invention to provide a logic gate circuit which performs logic functions involving the complement of one or more input signal.
It is another object of the present invention to perform logic functions involving the complement of one or more input signals without requiring separate inverter stages.
It is a further object of the present invention to provide a modified ECL logic gate which is useful in performing sequential and combinational logic functions and which does not require a separate inverter stage to permit the complement of one or more inputs to be incorporated in the logical operation.
It is yet another object of the present invention to perform logic functions involving the complement of an input signal without having to utilize collector dotting with a diode clamp.
It is an additional object of the present invention to provide a gate circuit to carry out logic functions involving the complement of one or more input signals without having to generate a separate V.sub.BB reference voltage.
It is another object of the present invention to carry out logic functions without having to distribute a reference voltage V.sub.BB, to separated logic gate circuits.